As a key technology for realizing reductions in size, weight, and thickness of electronic devices, various packaging technologies have so far been developed for semiconductor devices, in order to realize the high-density packaging of the semiconductor chips.
As a technology for the packaging structure of the semiconductor devices and for reducing the area necessary for packaging onto the motherboard, there is a pin insertion type package, such as DIP (Dual Inline Package). There have been developed a surface mount package (SOP (Small Outline Package)), with outer leads and also a package (BGA (Ball Grid Array)), in which outer output terminals are arranged in matrix on the lower surface of package.
As a technology for realizing the high-density packaging by reducing the area ratio of the package to the semiconductor chips, there have been made some attempts, such as narrow pitching of the outer output terminals by the minuteness of the substrate wiring and also reduction of the package size.
Further, there have been developed technologies, such as a multi-chip package and a chip-stacked package. In the multi-chip package, a plurality of semiconductor chips are gathered and packed in a single package. The chip-stacked package, as one kind of multi-chip package, has a plurality of semiconductor chips stacked therein for realizing the further high-density packaging. Of the multi-chip packages, a System In Package (SIP) has been developed, as one system which has realized the systematization by enclosing the plurality of semiconductor chips having different functions in a single package.
In this SIP technology, it is necessary to shape the wiring coupling between the chips for the reduction of the package, and there has been proposed a system for coupling the wiring using a relay member, to be called a silicon interposer (U.S. Pat. No. 4,615,189 and Japanese Unexamined Patent Publication No. Hei 5(1993)-102222).
However, if the relay member, such as a silicon interposer, is used, it causes a problem of increasing the cost in the designing and manufacturing of the relay member.
Japanese Unexamined Patent Publication No. 2008-177265 proposes a system for shaping the wiring coupling by providing relay members respectively between bonding pads and inner leads of a semiconductor device. For this relay member, there has been proposed a system for forming the member by stacking an electrically conducting layer on the surface of the semiconductor device. In this case, a problem is an increase in the cost of designing and manufacturing it.